Flash memory, both the NAND and NOR types, includes strings of NV memory elements or cells, such as floating-gate metal-oxide-semiconductor field-effect (FGMOS) transistors and silicon-oxide-nitride-oxide-silicon (SONOS) transistors. The fabrication of two-dimensional or planar flash memory devices is down to 10-nm lithography, and the reduction in scale has started to create potential issues as each NV memory element is getting smaller and physically closer to one another. In these NV memory elements, their charge trapping gates hold much fewer electrical charges due to the smaller scale. As a result, any small imperfection in the fabrication process may cause logic/memory states of the NV memory elements to become difficult to differentiate, which may result in a false reading of logic states. Moreover, control electrodes are getting so small and closely spaced that their effects, such as in biasing gates, may spread over more than one memory cells or strings, which may lead to unreliable reading and writing of data.
To overcome the limitations of available area on a semiconductor substrate, in 3-D or vertical geometry, NV memory cell strings are oriented vertically and NV memory cells are stacked on a semiconductor substrate. Accordingly, memory bit density is much enhanced compared to the two-dimensional (2-D) geometry having a similar footprint on the substrate.
In 3-D NV memory cell strings, channels are disposed inside openings formed in a dielectric/gate stack on a substrate. In certain applications, channels are mainly composed of polycrystalline silicon (Poly-Si), allowing electric current (charge carriers) to flow along the channels. Poly-Si channels may include silicon crystals of small grain sizes, contributing to more severe potential defects such as grain boundaries. Defects such as grain boundaries may cause charge carriers to scatter. As a result, the current flowing along channels may be reduced significantly. In 3-D memory cell strings, such as 3-D NAND, the reduction in reading current may affect the margin for read operations adversely. Moreover, in order to maintain a threshold reading or on-current, the number of layers in the dielectric/gate stack will be restricted, which in turn limit the number of memory cells (FGMOS, SONOS, etc.) in one NV memory string.